In a computer processing system, operation speeds of dynamic random access memories (DRAMs) used as main memories have been increased, but are still low compared with operation speeds of microprocessors. This discrepancy creates a wait time of the microprocessor and does not allow fast data processing, as the slower access time and cycle time of the DRAM form a bottleneck that affects the performance of the whole system.
In order to eliminate a difference in the operation speed between the DRAM and microprocessor, synchronous memory devices operable in synchronization with a clock signal have recently been developed, which has enabled SDRAMs to be used as main memories for fast microprocessors. In the SDRAM, introducing of external signals, i.e., address signals, control signals, and input/output data, is carried out in synchronization with a clock signal which is the system clock provided by the microprocessor. Since the external signals are introduced into the SDRAM device in synchronization with the whole system clock signal, it is not necessary to take into consideration a margin for skew of these external signals, and therefore an internal operation can be started rapidly. And since input and output data are transferred therein in synchronization with the clock signal, the accessing speed of data corresponds to the clock signal, allowing fast data transmission to be attained.
In order to enhance the accessing speeds to be more than those of single-data-rate SDRAMs, there have been proposed double-data-rate SDRAMs. These are accessible in response to each transition of the clock signal, i.e., responding to not only rising edges of the clock signal, but also to its falling edges.
One of the attractive functions of the SDRAM is that continuous bits per data input/output terminal make an access speed of data be more enhanced, i.e., a pipelined SDRAM. A burst length of the pipelined SDRAM is defined as the number of data bits continuously transferred to one input/output terminal in a sensing cycle (or a RAS cycle). The burst length is an important parameter or factor for determining a capacity of data read-out in one sensing cycle in the synchronous memory device. For both the single- and double-data-rate SDRAMs, performance of a data transmission in the SDRAM is mostly dependent upon controlling and optimizing the burst length or relevant accessing features such as a bypass architecture, in correspondence with the clock signal. In general, the burst length is flexible to different designer options, and its choice is related to the choice of the operation frequency of the clock signal.
FIG. 1 shows an exemplary electrical circuit for performing a data transmission in a synchronous memory device. The circuit includes a pad 1, input registers 2 and 3, multiplexer 4, and an output driving transistor 5. Pad 1 transfers external input data to the registers and output data driven by transistor 5 to an external circuit (not shown, out of the device). The registers 2 and 3 receive input reference signals, and store the input data to be applied to internal circuits in response to a pair of complementary clock signal CLK and CLKB (suffix "B" of a signal name means the counter-logic of the signal, and is marked with over-bar in the corresponding drawing). Multiplexer 4 applies data generated from the internal circuits to gate of transistor 5 in response to the pair of clock signals CLK and CLKB.
A synchronous burst pipelined memory having the late-write and double-data-rate (DDR) features writes data into memory cells at least one clock cycle after the addresses and control inputs have been presented. The memory can access data in response to both rising and falling edges of a clock signal CLK (or CLKB).
FIG. 2 is a timing diagram for explaining a problem encountered in a conventional pipelined burst memory, with the double-data-rate and late-write features in the case where a write operation is followed by a read operation without any vacant or no-operation (NOP) cycle therebetween. For simplicity, the problem will be discussed assuming the memory device operates in the burst length of 2.
Referring to FIG. 2, external addresses ADD are taken into the device in synchronization with a rising edge of clock signal CLK (i.e., a system clock). Specifically, external addresses A and B for two double-data-rate (DDR) write operations are introduced into the device at rising edges of the first and second cycles, respectively, of clock signal CLK. Then, input data DA0 and DA1, and DB0 and DB1 are applied to input buffer circuits (not shown) of the device from the second cycle of clock signal CLK, owing to the late-write feature. Data DA0 and DA1 correspond to address A, and DB0 and DB1 to B. Each set of the input data (DA0 and DA1, or DB0 and DB1) is accessed at both rising and falling edges of clock signal CLK, i.e., the double-data-rate mode.
A limitation of the prior art device is that a read cycle cannot start right after a write cycle. Indeed, a vacant (also known as "dummy") cycle must elapse for a write recovery. More specifically, if a read address C for a single-data-rate (SDR) read operation in a ready cycle were to be started just after the write cycle of address B without an interposing dummy cycle as shown in FIG. 2, it is impossible to write the input data bits DA1, DB0, and DB1 because of the write recovery. Only DA0 will be written. Therefore, even though the input data bits DA1, DB0, and DB1 are successfully taken into the device, they can not be written into memory cells selected by the addresses A and B during a write recovery period.
In the above case, in the event that the read address C is identical with the write address A or B, it is desirable to bypass the data DA1, DB0, or DB1 as output data corresponding to the read address C. It is very difficult, however, to realize a bypass control logic for such a conventional burst double-data-rate memory with flexible burst modes, in which the burst length can be changed.